The present invention relates to a semiconductor device and a method of producing the same and, more particularly, to a method of producing an FET (Field Effect Transistor) whose gate electrode has a minimum of fringe capacitance.
To enhance the high-speed operation of a logic LSI or similar semiconductor device, it is necessary to reduce parasitic capacitances which impair the driving ability. However, the problem with a conventional semiconductor device is that a fringe capacitance generated in a gate electrode slows down the circuit operation. The fringe capacitance may be reduced if, use is made of an organic insulation film or similar material having a lower dielectric constant than a silicone oxide film. However, an organic insulation film having low heat resistance and small dielectric constant is not applicable to side walls surrounding the gate, considering heat treatment. Alternatively, cavities may be formed in the side walls, as taught in Japanese Patent Laid-Open Publication No. 1-286363 or No. 7-193233. With the cavity scheme, however, it is impossible to expose the upper portion of the gate electrode or the upper portions of source and drain regions to the outside while keeping the top of the cavities covered with an oxide film. Therefore, silicidation for reducing the parasitic resistances of the gate electrode and source and drain regions is not practicable.
Controlling a short channel effect is another important consideration in the semiconductor devices art. To reduce the short channel effect, it is a common practice to form a gate electrode containing an impurity. A source region, a drain region and a pocket structure adjoin the gate electrode. The pocket structure, however, increases the junction capacitance of the drain region. This, coupled with the miniaturization of semiconductor devices, aggravates the influence of the parasitic capacitances on the device characteristic. To prevent the junction capacitance of the drain region from increasing, ions may be implanted between a gate electrode and silicide source and drain regions, as taught in "IEEE TRANSACTION ON ELECTRON DEVICES", VOL. 42, NO. 1, JANUARY 1995, pp. 78-86. This kind of method, however, has another problem that because silicide is susceptible to heat, the impurity implanted after a silicide process cannot be sufficiently treated by heat.
Assume that a semiconductor device is subjected to heat treatment for causing an impurity to be evenly distributed in a gate electrode, and for activating the impurity in a source and a drain region. Then, if the heat treatment is short, the impurity in the gate electrode cannot be evenly distributed and prevents the resistance of the electrode from being lowered to a sufficient degree. Conversely, if the heat treatment is excessive, the impurity in the source and drain regions is scattered into a channel region, rendering the short channel effect conspicuous. In addition, the impurity in the gate electrode is scattered into the channel region via a gate insulation film, varying the threshold value.